The present invention relates to a semiconductor device and a technology for manufacturing the same and, more particularly, to a technology which is effective when applied to a semiconductor device in which a transistor is formed on a compound semiconductor substrate and to a technology for manufacturing the same.
Japanese Unexamined Patent Publication No. 2003-273355 (Patent Document 1) discloses a technology which forms a field stopper layer (n+-type channel stopper layer) for stopping depletion in the peripheral edge portion of a semiconductor chip and forms an electrode on the field stopper layer.
Japanese Unexamined Patent Publication No. Hei 11(1999)-102917 (Patent Document 2) discloses a technology which forms a channel stopper region composed of a shallow n-type diffusion layer in the surface region of an n−-type epitaxial layer along the outer edge of a substrate and forms a channel stopper electrode over the channel stop region.
Japanese Unexamined Patent Publication No. 2003-101039 (Patent Document 3) discloses a technology which forms a channel stopper region composed of an n+-type heavily doped impurity layer in the peripheral edge portion of a semiconductor chip. On the channel stopper layer, a third electrode is provided to be electrically coupled to a second electrode formed on the back surface of the semiconductor chip. It is stated that, with the channel stopper region, it is possible to prevent the channel from expanding out of an element. It is also stated that the channel stopper region which is electrically coupled to the third electrode is provided to fix the surface potential of a semiconductor substrate and has the effect of preventing the degradation of breakdown voltage when a depletion layer reaches the channel stopper region. It is stated herein that the n+-type impurity in the channel stopper region may also be a p+-type impurity.
Japanese Unexamined Patent Publication No. 2004-158603 (Patent Document 4) discloses a technology which provides a p+-type channel stopper region in the element peripheral portion of a semiconductor chip and forms an electrode in the p+-type channel stopper region.
Japanese Unexamined Patent Publication No. Hei 9 (1997)-283754 (Patent Document 5) discloses a technology which forms a low-resistance n-type end portion layer in the surface of an n-type base layer in the outer terminal portion of a junction termination region to surround a trench. In addition, a ring-shaped end portion electrode is disposed to come in contact with the n-type end portion layer. It is stated that the surface of the junction termination region between a cathode electrode and the ring-shaped end portion electrode is covered with a thick insulating layer.
Japanese Unexamined Patent Publication No. 2005-203548 (Patent Document 6) discloses a technology which forms a diffusion layer as a guard ring portion in the peripheral edge portion of a semiconductor chip.
Japanese Unexamined Patent Publication No. Hei 07 (1995)-201855 (Patent Document 7) discloses a technology pertaining to a semiconductor device having a long and thin conductor film such as a guard ring used to improve, e.g., moisture resistance in the region between the peripheral edge portion of a semiconductor chip and wiring pads. The publication discloses the technology which reduces an external stress causing a crack in the guard ring in the mold encapsulation of the semiconductor chip and lessens characteristic failures resulting from the crack to allow an improvement in moisture resistance. It is stated that, specifically, the guard ring composed of a conductive film and provided in the region between the peripheral edge portion of the semiconductor chip and the wiring pads is formed in a meandering or curved pattern.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2006-273355    [Patent Document 2]    Japanese Unexamined Patent Publication No. Hei 11(1999)-102917    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2003-101039    [Patent Document 4]    Japanese Unexamined Patent Publication No. 2004-158603    [Patent Document 5]    Japanese Unexamined Patent Publication No. Hei 09 (1997)-283754    [Patent Document 6]    Japanese Unexamined Patent Publication No. 2005-203548    [Patent Document 7]    Japanese Unexamined Patent Publication No. Hei 07 (1995)-201855